Digital Core Design

Digital Core Design


Targets: Automotive, Motor Control

Digital Core Design DRPIC1655X Block Diagram

The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP (intellectual property) core, with fast dual ported memory. The core has been designed with a special concern towards low power consumption. The DRPIC1655X soft core is software compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses.

The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. Most instructions are executed within 1 system clock period, except instructions that directly operate on the program counter PC (GOTO, CALL, RETURN) because this requires a pipeline flush. This operation takes additional one clock cycle.

The DRPIC1655X targets applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices, and telecom processors. A built-in power save mode make this core suitable for applications where power consumption is critical.

Each of the DCD's PIC Core has built-in support for the DCD Hardware Debug System called DoCD. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). The DRPIC165X comes with a fully automated testbench and a complete set of tests

DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories.