E2V

E2V


PC7xx

Targets: Computers & Peripherals, Industrial, Military & Aerospace, Motor Control

The PC755 and PC745 Power Architecture microprocessors are high-performance, low-power, 32-bit implementations of the Power Architecture RISC architecture, targeting embedded applications. The PC755 and PC745 microprocessors differ only in that the PC755 features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC745 is a drop-in replacement for the Power Architecture 740 microprocessor and is also footprint and user software code compatible with the Power Architecture 603e microprocessor. PC755/745 microprocessors provide on-chip debug support and are fully JTAG-compliant. The PC745 microprocessor is pin compatible with the TSPC603e family.

The PC7410 microprocessor uses the fourth (G4) full implementation of the Power Architecture RISC architecture. It is fully JTAG-compliant. The PC7410 maintains some of the characteristics of G3 microprocessors: The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units. The microprocessor provides four software controllable power-saving modes and a thermal assist unit management. The microprocessor has separate 32-kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags. In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec technology instruction set. The latency is equal for double-precision and single-precision floating-point operations involving multiplication.

The PC7447A host processor is a 32-bit implementations of the PowerPC RISC architecture combined with a full 128-bit implementation of Freescale's AltiVec technology. This microprocessor targets embedded computing and signal processing applications. The PC7447A features 512-kbytes of on-chip L2 cache. The PC7447A microprocessor has no backside L3 cache, allowing for a smaller package designed as a pin-for-pin replacement for the PC7447 microprocessor. This device benefits from a silicon-on-insulator CMOS process technology. The core is a superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to the main memory and other system resources.

The PC7457 implements the fourth generation (G4) microprocessors from Freescale. The PC7457 implements the full Power Architecture 32-bit architecture and is targeted at networking and computing systems applications. The PC7457 consists of a processor core, a 512-kbyte L2, and an internal L3 tag and controller that support a glueless backside L3 cache through a dedicated high-bandwidth interface. The core is a superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1-, 2-, or 4-Mbytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4-Mbytes of SRAM, a maximum of 2-Mbytes may be used as cache; the remaining 2-Mbytes must be private memory.

The PC7448 is a high-performance processor manufactured on 90 nanometer silicon-on-insulator (SOI) process technology. The MPC7448 operates between 600 MHz and in excess of 1.5 GHz, contains a full megabyte of L2 cache, and offers enhanced power management capabilities. PC7448 processors target pervasive computing, embedded network control, and signal processing applications. The PC7448 includes the same 128-bit AltiVec vector execution unit as found in previous MPC74xx devices, but with the enhanced support for out-of-order instructions. AltiVec computational instructions are executed in the four independent, pipelined AltiVec execution units.