Design Support

The eSi-Connect IP (intellectual property) suite provides simple to integrate AMBA APB 3 peripherals from off-chip serial interfaces such as I²C, SPI and UART to control functions including timers, real-time clock, watchdog and GPIO. EnSilica provides advanced peripherals such as a 10/100 Ethernet MAC and a programmable multi-channel FIR filter. The blocks are configurable and provided with low-level software drivers suitable for real-time SoC deployment.

EnSilica offers two FPGA Embedded Evaluation Kits to evaluate eSi-RISC. These include a Cyclone III edition for Altera Quartus users and a Spartan 6 edition for Xilinx ISE users. Both include EnSilica's eSi-RISC Development Suite CD-ROM, example programs, documentation and tutorials.

The eSi-RISC Development Suite (v2.2) is based upon the industry standard GNU toolchain, which includes an optimizing C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. The customizable Eclipse IDE (Integrated Development Environment) can drive all these tools. The toolchain is available for both Windows and Linux hosts and for use at no cost.

Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints, and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly. Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.

It also allows developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics' ModelSim from the Eclipse GDB project debugger through a network socket connection. ModelSim conveniently displays disassembled instructions as text in the wave display which is especially helpful for SoC level hardware and software debugging.

Network application debugging is simplified with the integration of WinPcap into the eSi-RISC Development Suite's Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. This makes it possible, for instance, to run a Web Server on eSi-RISC with a live Ethernet connection serving web pages to a browser running on a remote computer.

A new port of FreeRTOS and lwIP TCP/IP network stack enhances operating system support.

To complement its IP, EnSilica provides the full range of front-end IC design services, from System Level Design, RTL coding and Verification through to either a FPGA device or the physical design interface (synthesis, STA, DFT) for ASIC designs.