Samsung Electronics

Samsung Electronics


Targets: Mobile & Wireless

Samsung Electronics S5PC110 Block Diagram

Samsung's S5PC110 is a 32-bit RISC CortexA8-based microprocessor targeting mobile phones and general applications. To provide optimized H/W performance for the 3G and 3.5G communication services, S5PC110 relies on a 64-bit internal bus architecture and hardware accelerators for tasks such as motion video processing, display control, and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG4, H.263, H.264 and decoding of MPEG2, VC1, Xvid. This H/W Encoder/Decoder supports real-time video conferencing and Analog TV out for NTSC and PAL mode, and HDMI output for HDTV.

The S5PC110 has an optimized interface to external memory capable of sustaining the memory bandwidth required in high-end communication services. The memory system has Flash/ROM external memory ports for parallel access and DRAM port for high bandwidth. Developers can configure the DRAM port to support mobile DDR, LPDDR2, and DDR2. The Flash/ROM Port supports SLC/MLC NAND Flash, NOR Flash, OneNAND and ROM type external memory.

To reduce total system cost, the S5PC110 includes hardware peripherals such as a TFT 24-bit true color LCD controller, camera interface, MIPI DSI and CSI-2, and System Manager for power management. The device includes a CF+/ATA interface, 4-channel UART, 24-channel DMA, 4- channel timers, 3-channel I²S, 2-channel S/PDIF, I²C bus interface, 3-channel HS-SPI, and configurable General I/O Ports. Other peripherals include USB Host 1.1 operating at full speed (12Mbps), USB OTG 2.0 operating at high speed (480Mbps), 3-channel SD Host and High Speed Multi-Media Card Interface, and PLLs for clock generation. POP (Package on Package) option with MCP is available for small form factor applications.