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Tiempo
Target Applications
Tiempo
Design Support
Tiempo offers a custom synthesis tool for use with its asynchronous cores. ACC (Asynchronous Circuit Compiler) is a synthesis tool that automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description language.
ACC takes as input a description written in SystemVerilog, which is perfectly suited for high-level modeling of clockless circuits, and generates as output a gate-level netlist in standard Verilog format. ACC can be inserted in any standard design flow, allowing designers to verify asynchronous and mixed asynchronous/synchronous circuits using any industry-standard simulation tools. The generated Verilog netlist can then be placed-and-routed using any standard back-end tool and verified with any electrical simulation tool.
ACC is available as an optional license attached to any Tiempo core IP (intellectual property) license, allowing developers to independently modify the purchased IPs as well as to synthesize their specific asynchronous blocks complementing these IPs.