Western Design Center

Western Design Center


Targets: Automotive, Consumer, Industrial, Medical

The W65C816S extends the 65xx technology family to handle 16–bit processing with a 16-Mbyte memory space while its emulation mode allows complete hardware and software compatibility with 64-kbyte 6502 designs. The New Direct Register and stack relative addressing provides capability for re–entrant, re–cursive and re–locatable programming.

The hard core IP (intellectual property) is in the industry standard GDSII format. The buffer ring has been designed with off-chip drivers, including latch-up and ESD protection. When the core is embedded, the off-chip buffer ring is replaced with OCB (On-Chip-Bus) interface ring. The abstract cell is the connecting points with labels that provide core verification and system verification. WDC's test programs require that all test pins be compared to the standard test vendors.

The W65C816 Soft Core is a RTL (Register Transfer Level) description in Verilog HDL (Hardware Description Language) and is a synthesizable model. This single clock logic architecture is technology independent. WDC's W65C816 Soft Core is designed to replace the industry standard W65C816 16-bit microprocessor and can be used as a drop-in replacement is ASIC's. It has been synthesized into the XC4085 FPGA technology from Xilinx. The behavioral model is equivalent to the original W65C816 hard core. The standard chip model includes the softcore and the buffer ring in RTL code. If the gate count needs to be minimized, developers should use the hard core of the W65C816C.