Cambridge Consultants

Cambridge Consultants


Targets: Consumer, General Purpose, Medical, Mobile & Wireless, Security, Other

Cambridge Consultants XAP4 Block Diagram

XAP4 is a 16-bit processor IP (intellectual property) core with a modern architecture designed for ASIC devices such as sensors, implants, wireless or mobile products that demand high performance, low energy and a small footprint. This processor meets the requirements set by medical products, communication systems, sensors and new pervasive or ubiquitous computing applications. It features software portability and good code density to save program memory size, minimize die area, and minimize energy consumption. At around 12k gates, the XAP4 performs at 0.7 DMIPS/MHz making it a replacement candidate for 8-bit processors in projects requiring higher performance or reduced cost.

A 16-bit XAP4 with 64-kbyte address capability offers adequate data precision and program size for many ASIC projects. It is efficient at running programs stored in Flash memory and its features support secure software updating and versatile in-place execution for lower memory cost and simplified software distribution. A XAP4 can often be used instead of a 32-bit core and memory, saving energy, and silicon cost.

XAP4's architecture, register set, instruction set and compiler are designed for efficient execution of programs written in C with high code density and reduced memory cost. The processor's rich set of over 170 instructions are represented in either 16- or 32-bit coding, chosen for high code density and fast execution. Many instructions map closely to C language constructs and there are multi-cycle instructions for block copy, block store, function entry and exit, math, and DSP. Software tools are hosted by the xIDE software development environment and include a GCC compiler, Binutils assembler and source-level debugger.

XAP4 supports applications that must run with high reliability and high security. Software executes in user mode or one of three privileged modes and the processor's hardware accelerates event handling and gives a very fast interrupt response, even when interrupts are nested. There is also support for common operating system primitives such as atomic instructions for system synchronization with semaphores. These features all provide XAP4 with the deterministic performance that is required by applications using a pre-emptive Real-Time Operating System.

XAP4a has a two-stage pipeline for low cost, low energy applications, delivering 0.7 Dhrystone MIPS per MHz. It enables many applications to run code directly from a Flash memory. For example, synthesized on a leading foundry's 90 nm CMOS logic (G) process the XAP4a runs at 215 MHz, when it will achieve 150 Dhrystone MIPS. At 16 MHz it could run code directly from Flash memory and still deliver 11 DMIPS. Energy consumption can be minimized by operating the core at a reduced clock frequency; at 1 MHz it consumes 20 µW of dynamic power on a 90 nm LP process.

XAP4a is a soft IP (intellectual property) core written in Verilog RTL for synthesis to either ASIC or FPGA for verification. The core is implemented in around 12k gates including all of its registers. It can be laid out in under 0.04 mm2 on 90 nm. ASIC designers using XAP4 will customize its Memory Management Unit to interface their peripherals and memories, typically Flash and RAM, and also the Interrupt Vector Controller to prioritize interrupts and generate an interrupt vector.