Cambridge Consultants

Cambridge Consultants


Targets: Consumer, General Purpose, Medical, Mobile & Wireless, Security, Other

Cambridge Consultants XAP5 Block Diagram

XAP5 is a 16/32-bit processor IP (intellectual property) core offering advanced computing functions at the low cost and energy consumption. It addresses the requirements of high volume and cost-sensitive chip designs such as sensors and wireless products, such as Bluetooth, ZigBee, GPS, RFID, and NFC. Target applications for XAP5 include automotive, communications, energy, medical devices, industrial, retail, metering, and consumer products. XAP5 offers high performance and low energy consumption in a small die area. Its modern architecture enables the optimization of both on-chip and off-chip memory systems. When programs are stored in Flash memory and energy use must be minimized, as in battery-powered systems, then a XAP5 processor is a good choice.

XAP5 has a 16-bit data bus to memory and an internal 32-bit bus between its registers and ALU. Registers are automatically paired for 32-bit data or 24-bit addresses, enabling XAP5 to simply manage up to 16-Mbytes of memory for programs and data. A processor with 16-bit data is the optimum choice for many applications, whereas 8-bit is inadequate and 32-bit is frequently unnecessary. Compared to a 32-bit core, a 16-bit processor and RAM is typically half the size and using a 16-bit stack saves energy on every access, i.e. every push or pop.

XAP5 features high density program code using a run-time mix of 16, 32 and some 48-bit instructions. Its short pipeline architecture maximizes instruction throughput at low clock speeds, enabling many programs to run directly from Flash memory and consume less energy. In-place execution of programs can be started from wherever they are located in memory so applications start immediately without having to first copy vectors or instructions to another memory. Multiple instances of programs can co-exist in memory providing a safe mechanism for Flash program updates whereby a download can complete safely and be checked for errors before restarting the system. XAP5 can dynamically relocate programs from physical storage to logical memory which allows programs to be distributed and stored anywhere in memory, ready for immediate in-place execution.

XAP5 hardware comprises the processor core and debug interface together with a Memory Management Unit and Interrupt Vector Controller, which are adapted to the required memory map with I/O registers and interrupts. The instruction set can be extended with an optional Custom Logic Unit. XAP5 has a unified program and data bus structure with all vectors, instructions, data and I/O registers appearing in a single 16-Mbyte Von Neumann address map. This is preferred for low cost, low energy systems as division of program memory into instructions and data remains entirely flexible so typical XAP5 chip designs can use only one 16-bit Flash and one 16-bit RAM.

The processor's software modes, event handling, deterministic behavior and configurable MMU facilitate techniques that support a secure software kernel managing isolated tasks in a trusted and high-reliability system using a pre-emptive RTOS.

The XAP5a is a two-stage pipeline processor core supplied in Verilog RTL for synthesis and layout in ASIC or verification in FPGA. It combines small size with high performance and will clock at 175 MHz on a 90 nm logic (G) process where it delivers 120 Dhrystone MIPS. At a lower clock frequency, say 16 MHz, it can deliver over 10 DMIPS and execute directly from Flash memory. In battery powered systems the XAP5a synthesis can be optimized for size instead of speed, to minimize energy consumption. Using a LP (low power) 90 nm process, XAP5a's dynamic power consumption can be as little as 25 µW per MHz, for a power efficiency of 27 DMIPS/mW. On 90 nm, the XAP5a core (including registers) occupies less than 0.05 mm2 of silicon, equal to about 18k gates.