Targets: General Purpose

ADRES (architecture for dynamically reconfigurable embedded systems) is a flexible processor architecture targeting mobile terminals. The ADRES processor architecture couples a VLIW processor with a coarse-grain-array (CGA) accelerator, through a shared central register-file.

This processor allows combining state-of-the-art power efficiency, with programmability in a high-level programming language (C). The DRESC compiler supports development for the ADRES architecture. The compiler supports c-code input for algorithms and an XML architecture template to describe the specific hardware instance of the CGA accelerator chosen by the designer. The designer can fully select the CGA matrix configuration including the array-matrix size, the functional units (FU), the type of FU connectivity, either local data or instruction registers. The compiler outputs compiled machine code for execution on the ADRES processor, a simulation file for cycle-accurate simulation, and a synthesizable VHDL file for ASIC design.

Several power optimization techniques and a multi-threading extension are part of the Licensed Technology.