Nios II/f (fast)

Targets: Medical, Other

Altera Nios II/f (fast) Block Diagram

Altera designed the Nios II/f "fast" processor core for highest performance. It is optimal for performance-critical applications as well as applications with large amounts of code and/or data, such as systems running a full-featured operating system. With performance over 250 DMIPS and over 200 MHz operation, the Nios II/f core is in the same performance class as an ARM9 core. The Nios II Embedded Design Suite, including the Eclipse-based Nios II Integrated Development Environment, supports development with the core.

The Nios II/f core features separate instruction and data caches, and it can access up to 2-Gbytes of external address space. It uses a 6-stage pipeline, and it includes dynamic branch prediction. The NIOS/f core supports optional tightly coupled memory for instructions and data, as well as options for hardware multiply, divide, and shift operations. The core supports up to 256 custom instructions. The JTAG debug module includes optional enhancements, including hardware breakpoints, data triggers, and real-time trace.

The Nios II/f core provides additional functionality and performance when targeting Altera device families with DSP (digital signal processing) blocks. In this case, the Nios II/f core provides hardware multiply circuitry that achieves single-cycle multiply operations. The multiply unit also functions as a single-cycle barrel shifter. The Nios II/f core provides optional divide circuitry that accelerates divide operations.

The broadcast industry has a wide range of requirements, but performance is near the top of that list. Nios II processors give broadcast design engineers a flexible processor that they can configure to meet performance requirements while optimizing for cost.

The Nios II processor allows developers in medical markets to build exact-fit systems that also protect their software investment. Nios II processors are customizable to include only the features and peripherals that are needed in any given design, and they provide the processor IP (intellectual property) that can be easily re-targeted to a newer FPGA, if the need arises.