Nios II/s (standard)

Targets: Automotive, Consumer, Industrial, Medical

Altera Nios II/s (standard) Block Diagram

Altera's Nios II/s "standard" processor core implements a small processor core without a significant trade-off in software performance. The Nios II/s core targets cost-sensitive, medium-performance applications, including those with large amounts of code and/or data, such as systems running a full-featured operating system. The Nios II Embedded Design Suite, including the Eclipse-based Nios II Integrated Development Environment, supports development with the core.

The Nios II/s core features an instruction cache and access to up to 2-Gbytes of external address space. It uses a 5-stage pipeline, and it includes static branch prediction. The NIOS/s core supports optional tightly coupled memory for instructions and data, as well as options for hardware multiply, divide, and shift operations. The core supports up to 256 custom instructions. The JTAG debug module includes optional enhancements, including hardware breakpoints, data triggers, and real-time trace.

The Nios II/s core provides additional functionality and performance when targeting Altera device families with DSP (digital signal processing) blocks. In this case, the Nios II/s core provides hardware multiply circuitry that achieves 3-cycle multiplication operations. The multiply unit also functions as a barrel shifter.

The Nios II processor allows developers in medical markets to build exact-fit systems that also protect their software investment. Nios II processors are customizable to include only the features and peripherals that are needed in any given design, and provide the processor IP (intellectual property) that can be easily re-targeted to a newer FPGA, if the need arises.