MIPS Technologies

MIPS Technologies


Targets: Automotive, Consumer, Industrial, Mobile & Wireless

MIPS Technologies M14KC Block Diagram

The MIPS32 M14Kc core incorporates the microMIPS code compression Instruction Set Architecture (ISA). microMIPS offers MIPS32 performance with equivalent 16-bit code density. The core features a high level of configurability and build-time options, and it maintains a high level of performance at lower clock frequencies across a wide range of geometries and standard processes.

A superset of the MIPS32 4KEc core, the M14Kc targets cost-sensitive embedded applications such as home entertainment, personal entertainment and home networking. The M14Kc core implements the MIPS32 Release 2 Architecture with a design that is based on the 4K microarchitecture. It incorporates an execution unit with a 5-stage pipeline, delivering performance efficiency of 1.5 DMIPS/MHz. The M14Kc core retains all of the features and functionality from the 4KEc core, including 32 General Purpose Registers (GPRs), high performance Multiply/Divide Unit (MDU) and optional coprocessor extension interfaces. It also includes the programmable instruction and data cache controller and Translation Lookaside Buffer Memory Management Unit (TLB MMU) from the 4KEc core.

The M14Kc core incorporates the microcontroller Application Specific Extension (ASE), which provides enhancements to interrupt handling logic, reduces interrupt latency and adds atomic-bit instructions. The M14Kc core also has advanced debug and profiling features and is supported by integrated software and hardware development tools and third party technologies.