Synopsys

Synopsys


DesignWare ARC 610D

Targets: Automotive, Communication & Wired, Consumer, Imaging & Video, Industrial, Mobile & Wireless

The 5-stage ARC 610D processor is suitable for SoC applications that combine conventional computation with signal processing algorithms. The core is designed for hard, real-time processing, where high speed and deterministic response are required. DSP options enable the 610D core to perform more functions and eliminate separate logic or DSP blocks from the SoC. Optionally, custom instruction extensions may be incorporated to achieve higher application performance. The configurable architecture allows SoC designers to include only the processor features that are required for their specific application. User-defined instruction and register extensions can deliver 5 to 100 times performance improvement for critical routines.

The built-in DSP features include instruction and register extensions that accelerate signal processing algorithms. The optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores. The ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets. The JTAG debug port and optional embedded hardware breakpoints facilitate software debug. The ARC 610D core is delivered as synthesizable RTL source code (Verilog), and it is fully compatible with industry standard design methodologies and tool flows.