Synopsys

Synopsys


DesignWare ARC 625D

Targets: Automotive, Communication & Wired, Consumer, Imaging & Video, Industrial, Mobile & Wireless

The configurable, 5-stage ARC 625D processor core is a full-featured, mid-range embedded core. It is designed as a complete processor solution for system-on-chips (SoCs) targeted at consumer, networking, automotive and other cost-sensitive markets. The ARC 625D core's flexible, configurable memory architecture makes it suitable for RTOS-based applications. DSP options enable it to perform more functions, eliminating separate logic or DSP blocks from the SoC. Optionally, custom instruction extensions may be incorporated to improve application performance levels. The configurable architecture allows SoC designers to include only the processor features that are required for their specific application and user-defined instructions and register extensions can deliver performance improvements for critical routines.

The memory design including caches and closely coupled (single-cycle) memories is suitable for RTOS-based applications. The built-in DSP features include instruction and register extensions that accelerate signal processing algorithms. The optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores. The ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets. The JTAG debug port and optional embedded hardware breakpoints facilitate software debug. The ARC 625D core is delivered as synthesizable RTL source code (Verilog), and it is fully compatible with industry standard design methodologies and tool flows.