Synopsys

Synopsys


DesignWare ARC 710D

Targets: Communication & Wired, Computers & Peripherals

The configurable 7-stage ARC 710D processor core is designed for high-performance embedded processing within system-on-chips (SoCs). The core is optimized for hard, real-time processing, where high speed and deterministic response are required. Small size, low power and configurable architectural features make the 710D core suitable for multi-core applications. DSP options enable the 710D core to perform more of the SoC's functions, eliminating separate logic or DSP blocks. Optionally, custom instruction extensions may be incorporated to improve application performance. The configurable architecture allows SoC designers to include only the processor features that are required for their specific application and user-defined instructions and register extensions can deliver performance improvements for critical routines.

The cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation. Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms. The optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores. The ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets. The inter-processor communication, multi-processor debug environment, and flexible interfaces enable multi-core designs. The JTAG debug port and optional embedded hardware breakpoints facilitate software debug. The ARC 710D core is delivered as synthesizable RTL source code (Verilog), and it is fully compatible with industry standard design methodologies and tool flows.