Targets: Automotive, Computers & Peripherals, Consumer

ARM ARM1156T2-S/ARM1156T2F-S Block Diagram

The ARM1156T2-S and ARM1156T2F-S macrocells are fully synthesizable processors extending the ARM11 family of cores. The ARM1156T2-S and ARM1156T2F-S cores are based on the ARMv6 instruction set architecture for high performance and real-time applications with the Thumb-2 enhancements for high code density and implement a nine-stage integer pipeline incorporating branch prediction technology.

The cores incorporate two AMBA 3.0 AXI 64-bit systems interfaces for high instruction and data throughput, augmented by an AMBA 3.0 AXI 32-bit I/O interface for effective access to local peripheral devices. The cores support the configuration of fault-tolerant memory technologies for on-chip caches and tightly coupled SRAM arrays enabling high reliability SoC (system-on-chip) solutions. The ARM1156T2F-S incorporates the ARM11 Vector Floating Point coprocessor.