Targets: Mobile & Wireless

ARM Cortex-A9 Block Diagram

The ARM Cortex-A9 processor is available as either a single core or configurable multicore processor, with both synthesizable or hard-macro implementations. The 2 GHz typical operation with the TSMC 40G hard macro implementation is scalable up to four coherent cores with advanced MPCore technology and an optional NEON media and/or floating point processing engine. The Cortex-A9 processors, built around the ARMv7 architecture, feature a dynamic length, multi-issue superscalar, out-of-order, speculating 8-stage pipeline to target consumer, networking, enterprise, and mobile applications.

The Cortex-A9 microarchitecture is delivered as either a scalable multicore processor or as a traditional single core processor. The architecture supports configurations of 16, 32, or 64-kbytes four-way associative L1 caches, with up to 8-Mbytes of L2 cache through the optional L2 cache controller.