Targets: Audio, Automotive, Consumer

ARM ARM926EJ-S Block Diagram

The ARM926EJ-S macrocell is fully synthesizable and it features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory interfaces, and a MMU (memory management unit). It also provides separate instruction and data AMBA bus compliant AHB interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16×32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution. A hardened implementation of the ARM926EJ is available from the ARM Foundry Program.

The 32/16-bit RISC architecture (ARMv5TEJ) and 32-bit ARM instruction set enables maximum performance and flexibility. The 16-bit Thumb instruction enables increased code density. The DSP instruction extensions and single cycle MAC along with the Jazelle technology enables single chip microcontroller, DSP, and Java implementations.

The Jazelle technology provides support for high-efficiency Java bytecode execution, ultra-low Java power consumption, and Java JIT compiler performance. The Jazelle support code does not result in increase in VM size.

The data and instruction cache sizes are flexible and the MMU supports operating systems including Symbian OS, Windows CE, and Linux. The instruction and data tightly coupled memory interfaces provide wait state support. The EmbeddedICE-RT logic enables real-time debug. The processor has industry standard AMBA bus AHB interfaces, and ETM interface for Real-time trace capability with ETM9 and an optional MOVE coprocessor that delivers video encoding performance.