Targets: General Purpose

ARM Cortex-M3 Block Diagram

The ARM Cortex-M3 processor has been designed 'from the ground up' to provide optimal performance and power consumption within a minimal memory system. To achieve this the core executes only the Thumb-2 instruction set. The design is based on a 3-stage pipeline Harvard architecture that maximizes memory utilization through the support of unaligned date storage, and single cycle atomic bit manipulation. The highly revised architecture implements hardware divide and single-cycle multiply. The ARM Cortex-M3 uses 33k gates for the processing core and 60k gates total, including many closed system peripherals.

The ARM Cortex-M3 processor reduces the number of pins required for debug from five to one, by implementing a Single Wire Debug. For system trace, the processor integrates an optional ETM alongside data watch points that can be configured to trigger on specific system events. To enable simple and cost effective profiling of these system events a SWV (Serial Wire Viewer) can export streams of standard ACSII data through a single pin. Flash Patch technology offers device and system developers the ability to patch errors in code from ROM to SRAM or Flash during both debug and run-time.

The Cortex-M3 processor integrates the core with a configurable interrupt controller to improve interrupt processing performance. In its standard implementation the NVIC supplies a NMI (Non-Maskable Interrupt) plus 32 general purpose physical interrupts with 8 levels of pre-emption priority, however through simple synthesis choices the controller can be configured down to a single physical interrupt or up to 244. The number of levels of preemptive priority can be configured at synthesis up to 255. Faster execution of ISR (Interrupt Service Routines) is accomplished by using hardware stacking of registers and the ability to exit and restart load-store multiple executions. This means that no assembler stubs are required to handle the movement of registers. Moving between active and pending interrupts has been simplified through the use of Tail-Chaining technology to replace serial stack Pop and Push actions that normally take over 30 clock cycles with a simple six cycle instruction fetch. To enhance low power designs the NVIC integrates three sleep modes, including a Deep Sleep function that may be exported to other system components to enable the entire device to be rapidly powered down.

The ARM Cortex-M3 processor has two optional components, the MPU (Memory Protection Unit) and the ETM (Embedded Trace Macrocell). The fine grain MPU design enables applications to implement security privilege levels, separating code, data and stack on a task-by-task basis.