Targets: Mobile & Wireless

ARM Cortex-A8 Block Diagram

The Cortex-A8 processor targets digital entertainment and mobile communication devices such as mobile phones, set-top boxes, gaming consoles, and navigation systems. With the ability to scale in speed from 600 MHz to greater than 1 GHz, the Cortex-A8 processor can meet the requirements for power optimized mobile devices needing operation in less than 300 mW and performance optimized consumer applications requiring 2000 Dhrystone MIPS. The ARM Cortex-A8 processor's pipeline architecture is based on dual, symmetric, in-order issue, 13-stage pipelines with advanced dynamic branch prediction and static scheduling to deliver 2.0 DMIPS/MHz.

The Cortex-A8 processor features Thumb-2 technology for enhanced code density and performance. The Thumb-2 instruction set combines 16- and 32-bit instructions to improve code density and performance. The original ARM instruction set consists of fixed-length 32-bit instructions, while the original Thumb instruction set employs 16-bit instructions.

Thumb-2 adds about 130 additional instructions to Thumb that removes the need to switch between ARM and Thumb modes in order to service interrupts, and to give access to the full set of processor registers. The resulting code maintains the traditional code density of Thumb instructions while running at the performance levels of 32-bit ARM code.

The Cortex-A8 processor also features NEON technology for multimedia and signal processing. This technology operates as a data processing engine attached to the end of the main processor pipeline and is able to process demanding applications such as VGA H.264 30fps video decode in less than 350MHz. Both the main pipeline and the NEON engine are supported directly by high-performance Level 1 (16- or 32-kbytes) and Level 2 (configurable from 64-kbytes to 2- Mbytes) caches that work together to minimize access latency, minimize external bus traffic, and support high bandwidth data streaming to NEON technology.

The Jazelle-RCT (Realtime Compilation Target) technology in the Cortex-A8 processor is an architecture extension that cuts the memory footprint of just-in-time (JIT) bytecode applications to a third of their original size. The smaller code size results in a performance boost and a reduction of power.

The Cortex-A8 processor also supports TrustZone technology that protects peripherals and memory against security attacks. A secure monitor within the core serves as a gatekeeper, switching the system between secure and nonsecure states. In the secure state, the processor runs "trusted" code from a secure code block to handle security-sensitive tasks such as authentication and signature manipulation.

The Cortex-A8 processor's performance and power efficiency is enabled by combining advanced technology such as the ARM Artisan AdvantageCE library with enhanced design flows supporting synthesis, structured, and custom design. The Cortex-A8 processor is supported by ARM's ecosystem of technology. Tools supporting the Cortex-A8 processor include: RealView system development tools, RealView Development Suite 3.0, AMBA Designer interconnect design tool, CoreSight debug and trace, AXI system level components, and the IEM (Intelligent Energy Manager).