Targets: General Purpose

Tensilica 106Micro Block Diagram

The Diamond Standard 106Micro is a cache-less controller that is suitable as a basic 32-bit controller. Although the Diamond 106Micro is small, it employs a 5-stage pipeline so it can achieve 250 MHz in 130G process and up to 400 MHz in 90G process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a high code density. The local, tightly-coupled instruction and data memory on the Diamond Standard 106Micro can be used to store performance-sensitive code and data, such as for interrupt handlers.

The Diamond 106Micro has an iterative, multi-cycle (non-pipelined) 32x32 multiplier. The processor uses a non-windowed 16-entry AR register file to keep area low and that potentially does better on applications that have deeply nested function calls, since it never throws an exception. The Diamond Standard 106Micro interrupt architecture includes an integrated interrupt controller with 15 interrupts, and an integrated timer. This simplifies system design since no external hardware is needed for these functions.

Development support for the Diamond 106Micro includes the standard development tools, including an ISS (instruction set simulator), debugger, and C-compiler that all run under Tensilica's Eclipse-based Xplorer development environment.