Xtensa LX3

Targets: General Purpose

Tensilica Xtensa LX3 Block Diagram

The Xtensa ISA (instruction set architecture) is a 32-bit RISC architecture featuring a compact instruction set optimized for embedded designs. The architecture has: a 32-bit ALU; 16, 32 or 64 general-purpose physical registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16-and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. On some processors, 64-bit VLIW encoding is utilized when efficient, and these 2- or 3-issue instructions are also modelessly intermixed with 16- and 24-bit instructions. This allows the Xtensa ISA to optimize the size of the program instructions by minimizing both the static number of instructions (the instructions that constitute the application program) and the average number of bits per instruction.

To address the growing speed disparity between standard cell logic and memories, the Xtensa LX3 processor features a configurable pipeline. Designers can select a configuration option for a 7-stage pipeline that adds two additional clock cycles for memory access if required by the application. While the Xtensa LX3 processor's standard 5-stage pipeline is efficient for many applications, designers employing large local memories or specialized low-power memories with longer access times will find advantages in moving to a longer pipeline, resulting in a higher system clock frequency.

The TIE (Tensilica instruction extension) language is used to describe new instructions, new registers and execution units, and new I/O ports that are then automatically added to the Xtensa LX3 processor. TIE is a Verilog-like language used to describe desired instruction mnemonics, operands, encoding and execution semantics. The Xtensa Processor Generator automatically builds a version of the Xtensa LX3 processor and the complete tool chain that incorporates the new TIE instructions.

The Xtensa LX3 processor implements Tensilica's FLIX (Flexible Length Instruction Xtension) architecture. FLIX is a configuration option that allows designer-defined instructions to consist of multiple, independent operations bundled into a 32-bit or 64-bit instruction word. Wide 32-or-64-bit FLIX instruction formats are seamlessly and modelessly intermixed with the base Xtensa ISA's existing 16-/24-bit instructions - there is no mode switch penalty to utilize a FLIX instruction.

The use of 24- and 16-bit instruction words, the use of compound instructions, the richness of the comparison and bit-testing instructions, zero-overhead-loop instructions, register windowing, and the use of encoded immediate values all contribute to the Diamond processors' small code size. Reducing code size results in smaller memory sizes and lower power.