Design Support

The Diamond Standard and Xtensa processor software development environments include complete compiler toolchain, instruction set simulator, performance analysis tools and project management tools.

Xplorer is a fully integrated GUI that incorporates all the software development tools for the Tensilica processors. Designers can use Xplorer to create, build, simulate, profile, debug, and analyze code targeted for Tensilica's processor. Xplorer DE is based on the Eclipse platform. Xplorer contains context-sensitive help, along with tutorials and sample workspaces that speed up code development. Built-in project management and version control mechanisms eliminates the need to maintain makefiles and provides a clean environment for new project builds.

Tensilica's XCC C/C++ compiler is an optimizing compiler with advanced optimizations such as profile-directed feedback compilation, inter-procedural analysis and optimizations, alias analysis, function in-lining, software pipelining, static single assignment (SSA) optimizations, and code generation techniques to reduce code size. When used with Xtensa processors, XCC is fully aware of user-defined instructions generated by the TIE (Tensilica instruction extension) compiler, which automatically updates XCC with knowledge of user-defined instructions. There is no designer intervention during the process of modifying and updating XCC by the TIE compiler.

The TIE language is a hybrid of the Verilog and C languages. A designer uses the TIE language to define new custom instructions to be included with the base Tensilica Xtensa processor architectures. These instruction set extensions, when run through the TIE compiler, simultaneously create the HDL for new hardware (execution units, register files, state variables, data types, bus widths, etc.) and modify the software development tools to make use of these extensions automatically.

The rest of the software development toolchain is based on standard GNU tools. The compiler front-end remains similar to the preprocessor in the GCC compiler -- hence the flags for the preprocessor remain the same. The assembler and linker also utilize the same flags as the GNU versions of the tools.

The GUI based debugger allows full system visibility into a developer's project. Source/assembly and hardware registers are visible while debugging an application. Multiple views of various system aspects can be simultaneously displayed within the Xplorer environment. The debugger interoperates seamlessly with the other development tools (compiler toolchain, instruction set simulator) to allow rapid code development.

The Xplorer environment enables graphical visualization of profiling results generated by Tensilica's pipeline-accurate ISS. Code developers can hence view accurate performance modeling information such as cache performance, cycle counts, branch penalties, exceptions, pipeline views, and tracing in tabular and graphical views. Additionally, an option from Tensilica, the XTMP (Xtensa Modeling Protocol) application programming interface is available to simulate systems that consist of multiple Tensilica processors.

The "Diamond Video Engine Controller" application note describes how to write basic control code to control video decoding functionality using the 388VDO Diamond Video Engine. This tutorial supplements the "Diamond 388VDO Software Guide" by providing a thorough explanation of how the API is used to set up and control theDiamond Video Engine to perform basic video decoding.

Double-precision floating point is used in applications that require precision greater than single precision floating point. In Tensilica processors, these operations are implemented with a software emulation library. The "Double-Precision Floating Point Emulation Acceleration" application note presents a small set of TIE instructions and states that can be used for speeding up the existing double-precision software emulation.

The "Emulation Flow for Xtensa Cores" application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system. This application note includes a demonstration example of an FPGA flow based upon Xilinx logic using RTL for the 108Mini Diamond core.

The "Audio Reference Design Guide Addendum: System Software Example" application note describes a system software example that performs back-to-back audio stream decoding across a variety of audio formats. This addendum is intended to teach a basic approach to developing audio application code for the Audio Reference Design.

The jtag.v module provided with Tensilica's Xtensa LX, Xtensa LX2, and Diamond configurations that include the On-Chip Debug option, is intended as a simple driver model for JTAG TAP. The "Extending the JTAG.v Module" application note explores a couple of possible extensions to this module: Adding support for new core instructions and modifying the jtag.v module to support multiple Xtensa cores.

The Xenergy energy estimation tool enables system architects, software developers, and TIE instruction designers to evaluate the power and energy dissipation characteristics of design choices and application code early in the development cycle for Xtensa and Diamond processors. The "Optimizing for Energy using the Xenergy Energy Optimizor Tool" application note examines the use models for Xenergy. It also demonstrates how to use Xenergy to optimize software applications, select the right Diamond processor or Xtensa configuration options, and add TIE instruction extensions, all with the goal of optimizing the total processor sub-system energy.

The "Fast OFDM on Xtensa Processors" application note looks briefly at fast signal processing for wireless modems. In particular, this application note describes the TIE language instructions that accelerate the complex FFT and FIR operations that dominate many OFDM channel modulation and demodulation systems.

The "Implementing A Mutex and Barrier Synchronization Library on Xtensa" application note describes how multiprocessor synchronization instructions can be used to implement a memory-based mutual exclusion (mutex) primitive. This enables tasks running on the different processors to synchronize with each other and safely access shared data. Included with this application note is the complete source code for a C/C++ library that implements an example mutex API as well as a barrier synchronization API.

The "Implementing FIFO Operations Using TIE Queues" application note provides TIE and C code that demonstrate how to implement standard FIFO (First In, First Out) operations using TIE queues. The FIFO operations described in this document include testing for a full or empty FIFO, pushing a value onto a FIFO, and popping a value from a FIFO. This application note also shows how to describe the C data type of the values carried by a FIFO to ensure correct and efficient code generation by the Xtensa C/C++ compiler. The application note and included sample TIE and C code serve as examples for users implementing TIE queues in their designs.

The "Convolutional Encoding and Decoding, Especially Viterbi Decoding, on Xtensa Processors" application note looks briefly at popular techniques for convolutional encoding and decoding, especially Viterbi decoding, and illustrates the power of a configurable processor in handling the performance-intensive signal processing demands of coding and decoding.

The "Xtensa Processor Extensions for Fast IP Packet Classification" application note presents how to achieve fast IP packet classification with a configurable processor. Packet classification requires multiple field matching such as the IP source address, IP destination address, source port number, destination port number, protocol number, differentiated service code point (DSCP) and more. To accelerate table lookups and bitmap manipulation, several customized instructions were developed to yield large performance improvements. By using two 200 MHz processors with a proper configuration, OC48 wire-speed packet classification can be achieved while matching on multiple fields with sophisticated rules of ranges and/or prefixes.