Targets: General Purpose

Tensilica 212GP Block Diagram

The Diamond Standard 212GP is a high-performance, fully synthesizable 32-bit RISC controller core. It is area and power efficient with a flexible local memory. Users can take advantage of Tensilica's lockable cache and attach any size single-cycle instruction or data SRAM up to 128-kbytes. Since Diamond 212GP target applications are controller related, the Diamond 212GP includes a non-maskable interrupt for critical system events and six levels of interrupts consisting of a combination of external, software, and timing interrupts.

Integrated arithmetic and DSP hardware support reduces the need to include a separate DSP in the system design. DSP support in the Diamond 212GP consists of a single-cycle 16x16-bit MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Additionally, there is support for zero overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. The Diamond 212GP supports 400 MHz operation in a 90nm G-type process. It is capable of handling any control plane and many DSP applications because of the built-in 32x32 multiplier and 32-bit integer divider.