Targets: General Purpose

Tensilica 108Mini Block Diagram

The Diamond Standard 108Mini is a fully synthesizable 32-bit RISC controller core. It is a small, cache-less RISC controller with tightly-coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance. The Diamond 108Mini features low-power consumption for portable applications. Although the Diamond 108Mini is smaller in die area, its performance is 1.34 Dhrystone MIPS/MHz at 420 MHz in a 90nm G process. It also achieves high performance on DSP applications and engine and motor control applications because of the built-in 32x32 multiplier and 32-bit integer divider.

The Diamond 108Mini delivers fast and flexible interrupt handling with the availability of low interrupt latency and a rich interrupt architecture. The processor has deterministic behavior for applications with hard real-time constraints. 32 base registers are windowed 16 at a time, which enables faster context switching due to reduced stack operations. Local single-cycle SRAM allows time critical code to be placed near the CPU. Dual local data SRAM enables the processor access to one bank of RAM while an external DNA operation can operate on the other bank. Separate instruction and data memory interfaces lead to lower contention than unified interface architectures.