Targets: General Purpose

Tensilica 570T Block Diagram

The Diamond Standard 570T combines a 5-stage pipeline with a 3-issue VLIW architecture. Due to the Diamond 570T's flexible base architecture, 16-, 24-, and compound 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching. The compiler automatically creates 64-bit VLIW instruction bundles if instructions can be issued simultaneously; otherwise, a single 16/24-bit instruction is issued. This capability increases code density, reducing the amount of on-chip cache or memory required for storage of instructions.

The Diamond 570T includes standard DSP instructions to increase performance of numerically intensive applications, plus a 32x32 multiplier and 32-bit integer divider. Example DSP instructions include: zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. Additionally, a MAC unit enables high performance on inner loops requiring fast multiplication.

The Diamond 570T also includes 32-bit input/output GPIO ports and 32-bit input/output FIFO interfaces, which can be used to connect to standard FIFOs for fast communication with other RTL blocks, devices, and processors without ever using the system bus to maximize throughput.